8 channel, 16 bit Verilog Multiplexer

[code title=”mux_8to1_16bit.v” collapse=”true”]
// 8 channel mux
// BK Turley

timescale 1ns/100ps

module mux_8to1_16bit(out, sel, in0, in1, in2, in3, in4, in5, in6, in7);

input [2:0] sel;
input [15:0] in0;
input [15:0] in1;
input [15:0] in3;
input [15:0] in4;
input [15:0] in5;
input [15:0] in6;
input [15:0] in7;
output [15:0] out;

reg [15:0] out;

always @( sel or in0 or in1 or in2 or in3
or in4 or in5 or in6 or in7)

case (sel)
3'b000 : out <= in0;
3'b001 : out <= in1;
3'b010 : out <= in2;
3'b011 : out <= in3;
3'b100 : out <= in4;
3'b101 : out <= in5;
3'b110 : out <= in6;
3'b111 : out <= in7;
default : out <= in0; // channel 0 is selected on high impedence input
endcase

endmodule
[/code]

[code title="mux_8to1_16bit_tb.v" collapse="true"]

// B. Turley
//mux_8to1_16bit_tb.v

timescale 1ns/100ps

module mux_8to1_16bit_tb;

reg [2:0] mux_sel;
reg [15:0] mux_in0;
reg [15:0] mux_in1;
reg [15:0] mux_in2;
reg [15:0] mux_in3;
reg [15:0] mux_in4;
reg [15:0] mux_in5;
reg [15:0] mux_in6;
reg [15:0] mux_in7;
wire [15:0] mux_out;

mux_8to1_16bit mux(mux_out, mux_sel, mux_in0, mux_in1, mux_in2,
mux_in3, mux_in4, mux_in5, mux_in6, mux_in7);

initial begin

$dumpfile("./mux_8to1_16bit.dmp");
$dumpvars(2, mux_8to1_16bit_tb);

mux_in0 <= 16’h0000;
mux_in1 <= 16’h0001;
mux_in2 <= 16’h0002;
mux_in3 <= 16’h0003;
mux_in4 <= 16’h0004;
mux_in5 <= 16’h0005;
mux_in6 <= 16’h0006;
mux_in7 <= 16’h0007;
mux_sel <= 3’b000;

#20 mux_sel <= 3’b001;
#20 mux_sel <= 3’b010;
#20 mux_sel <= 3’b011;
#20 mux_sel <= 3’b100;
#20 mux_sel <= 3’b101;
#20 mux_sel <= 3’b110;
#20 mux_sel <= 3’b111;
#20 mux_sel <= 3’b000;

#20 $finish;
end
endmodule

[/code]

Verilog model of a control unit for the SEP (Simple Educational Processor)

[code title=”View Code: sep_cu.v” collapse=”true”]
module cu(clk, reset, IRin, C, SC_Val);

input clk, reset;
input [15:0] IRin;

output [14:0] C;
output [3:0] SC_Val;

wire [7:0] D;
wire [7:0] T;

wire w1;

decoder_df IR_decoder(IRin[14],IRin[13],IRin[12], 0, D);
decoder_df Cnt_decoder(SC_Val[2],SC_Val[1],SC_Val[0], 0, T);
SecCounter SC(SC_Val, clk, w1, 0);

or (w1,C[8],reset);

assign
C[0] = T[0] | T[2] | (~D[7] & IRin[15] & T[3]),
C[1] = D[4] & T[4],
C[2] = T[1],
C[3] = D[2] & T[4],
C[4] = D[2] & T[5],
C[5] = T[1],
C[6] = T[1] | (~D[7] & IRin[15] & T[3]) | (D[2] & T[4]),
C[7] = D[3] & T[4],
C[8] = (D[2] & T[5]) | (D[3] & T[4]) | (D[4] & T[4]),
C[9] = T[1] | T[2] | T[3] | (T[4] & D[2]) | (T[4] & D[3]),
C[10] = T[0] | T[1] | T[3] | (T[4] & D[2]),
C[11] = T[1] | T[2] | T[3] | (T[4] & D[2]) | (T[4] & D[4]),
C[12] = 0,
C[13] = 0,
C[14] = 0;

endmodule

module decoder_df (A,B,C,E,D);
input A,B,C,E;
output [7:0] D;
assign D[0] = (~A & ~B & ~C & ~E),
D[1] = (~A & ~B & C & ~E),
D[2] = (~A & B & ~C & ~E),
D[3] = (~A & B & C & ~E),
D[4] = (A & ~B & ~C & ~E),
D[5] = (A & ~B & C & ~E),
D[6] = (A & B & ~C & ~E),
D[7] = (A & B & C & ~E);
endmodule

module SecCounter(count, CLK, RST, INC);
parameter n = 4;

output [n-1:0] count;
reg [n-1:0] count;
input CLK;
input RST;
input INC;

// Increment count on clock
always @(negedge CLK)
if (RST)
count = 0;
else if (~INC)
count = count + 1;

endmodule
[/code]