Verilog model of a control unit for the SEP (Simple Educational Processor)

[code title=”View Code: sep_cu.v” collapse=”true”]
module cu(clk, reset, IRin, C, SC_Val);

input clk, reset;
input [15:0] IRin;

output [14:0] C;
output [3:0] SC_Val;

wire [7:0] D;
wire [7:0] T;

wire w1;

decoder_df IR_decoder(IRin[14],IRin[13],IRin[12], 0, D);
decoder_df Cnt_decoder(SC_Val[2],SC_Val[1],SC_Val[0], 0, T);
SecCounter SC(SC_Val, clk, w1, 0);

or (w1,C[8],reset);

assign
C[0] = T[0] | T[2] | (~D[7] & IRin[15] & T[3]),
C[1] = D[4] & T[4],
C[2] = T[1],
C[3] = D[2] & T[4],
C[4] = D[2] & T[5],
C[5] = T[1],
C[6] = T[1] | (~D[7] & IRin[15] & T[3]) | (D[2] & T[4]),
C[7] = D[3] & T[4],
C[8] = (D[2] & T[5]) | (D[3] & T[4]) | (D[4] & T[4]),
C[9] = T[1] | T[2] | T[3] | (T[4] & D[2]) | (T[4] & D[3]),
C[10] = T[0] | T[1] | T[3] | (T[4] & D[2]),
C[11] = T[1] | T[2] | T[3] | (T[4] & D[2]) | (T[4] & D[4]),
C[12] = 0,
C[13] = 0,
C[14] = 0;

endmodule

module decoder_df (A,B,C,E,D);
input A,B,C,E;
output [7:0] D;
assign D[0] = (~A & ~B & ~C & ~E),
D[1] = (~A & ~B & C & ~E),
D[2] = (~A & B & ~C & ~E),
D[3] = (~A & B & C & ~E),
D[4] = (A & ~B & ~C & ~E),
D[5] = (A & ~B & C & ~E),
D[6] = (A & B & ~C & ~E),
D[7] = (A & B & C & ~E);
endmodule

module SecCounter(count, CLK, RST, INC);
parameter n = 4;

output [n-1:0] count;
reg [n-1:0] count;
input CLK;
input RST;
input INC;

// Increment count on clock
always @(negedge CLK)
if (RST)
count = 0;
else if (~INC)
count = count + 1;

endmodule
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