8 channel, 16 bit Verilog Multiplexer

[code title=”mux_8to1_16bit.v” collapse=”true”]
// 8 channel mux
// BK Turley

timescale 1ns/100ps

module mux_8to1_16bit(out, sel, in0, in1, in2, in3, in4, in5, in6, in7);

input [2:0] sel;
input [15:0] in0;
input [15:0] in1;
input [15:0] in3;
input [15:0] in4;
input [15:0] in5;
input [15:0] in6;
input [15:0] in7;
output [15:0] out;

reg [15:0] out;

always @( sel or in0 or in1 or in2 or in3
or in4 or in5 or in6 or in7)

case (sel)
3'b000 : out <= in0;
3'b001 : out <= in1;
3'b010 : out <= in2;
3'b011 : out <= in3;
3'b100 : out <= in4;
3'b101 : out <= in5;
3'b110 : out <= in6;
3'b111 : out <= in7;
default : out <= in0; // channel 0 is selected on high impedence input
endcase

endmodule
[/code]

[code title="mux_8to1_16bit_tb.v" collapse="true"]

// B. Turley
//mux_8to1_16bit_tb.v

timescale 1ns/100ps

module mux_8to1_16bit_tb;

reg [2:0] mux_sel;
reg [15:0] mux_in0;
reg [15:0] mux_in1;
reg [15:0] mux_in2;
reg [15:0] mux_in3;
reg [15:0] mux_in4;
reg [15:0] mux_in5;
reg [15:0] mux_in6;
reg [15:0] mux_in7;
wire [15:0] mux_out;

mux_8to1_16bit mux(mux_out, mux_sel, mux_in0, mux_in1, mux_in2,
mux_in3, mux_in4, mux_in5, mux_in6, mux_in7);

initial begin

$dumpfile("./mux_8to1_16bit.dmp");
$dumpvars(2, mux_8to1_16bit_tb);

mux_in0 <= 16’h0000;
mux_in1 <= 16’h0001;
mux_in2 <= 16’h0002;
mux_in3 <= 16’h0003;
mux_in4 <= 16’h0004;
mux_in5 <= 16’h0005;
mux_in6 <= 16’h0006;
mux_in7 <= 16’h0007;
mux_sel <= 3’b000;

#20 mux_sel <= 3’b001;
#20 mux_sel <= 3’b010;
#20 mux_sel <= 3’b011;
#20 mux_sel <= 3’b100;
#20 mux_sel <= 3’b101;
#20 mux_sel <= 3’b110;
#20 mux_sel <= 3’b111;
#20 mux_sel <= 3’b000;

#20 $finish;
end
endmodule

[/code]

Leave a Reply

Your email address will not be published. Required fields are marked *