Verilog 16 bit register with testbench.

[code title=”reg_16bit.v code” collapse=”true”]//16 bit Register by B Kyle Turley
//Verilog

timescale 1ns/100ps

module reg_16bit (out, in, load, clear, clk);
input   [15:0]   in;
input           load;
input           clear;
input           clk;
output  [15:0]   out;

reg     [15:0]   Q;

always @(posedge clk)
begin
if(clear == 1'b1) // If clear is high, it has priority
Q <= 16'b000000000000000;
else if(load == 1'b1) // load has the next highest
Q <= in;
else
Q <= Q;
end

/* Set output equal to the internal state */
assign out = Q;

endmodule

[/code]

[code title="reg_16bit_tb.v code" collapse="true"]timescale 1ns/100ps

module reg_16bit_tb;

reg [15:0] reg_input;
reg reg_load;
reg reg_clear;
reg clk;

wire [15:0] reg_out;
integer fid;

reg_16bit register(reg_out, reg_input, reg_load, reg_clear, clk);

initial begin
clk = 1’b0;
forever #10 clk <= ~clk;
end

initial begin

fid = $fopen("./reg_16bit.out");
$fmonitor(fid, $time, " out = %h, in = %h, load = %b, clear = %b",
reg_out, reg_input, reg_load, reg_clear ) ;

$dumpfile("./reg_16bit.dmp");
$dumpvars(2, reg_16bit_tb);

reg_clear <= 1’b1;
reg_load <= 1’b0;
reg_input <= 16’hABCD;
#20 reg_clear <= 1’b0;
#20 reg_load <= 1’b1;
#20 reg_load <= 1’b0;
#20 reg_input <= 16’h1234;
#20 reg_load <= 1’b1;
#20 reg_load <= 1’b0;
reg_input <= 16’h0000;
reg_clear <= 1’b1;
#20 reg_clear <= 1’b0;
#20 $finish;
end

endmodule
[/code]

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