Verilog Clock and Oscillator

The clock signal is essential when designing sequential circuits, the following two code examples demonstrate how to produce a clock signal for your FPGA projects. These modules could also be used to produce square wave oscillations for other purposes such as audio tones.

[sourcecode]

module Clk_Signal (clock); // Verilog 1995
parameter delay = 5;
output clock;
reg clock;</code>

initial begin
clock = 0;
forever #delay clock = ~clock;
end
endmodule

module Clk_Signal #(parameter delay = 5) (output reg clock); // V2001

initial forever #delay clock = ~clock;
endmodule

[/sourcecode]

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