convert integer to any base C++

this function is capable of converting integers to any base format 2-16. this includes binary, octal, and hexadecimal. adding larger bases is as simple as lengthening the alpha string.

Some Great Examples of recursion C++

This little program demonstrates the recursion technique in three different settings.  It includes recursive algorithms to search an array, reverse a number, and find the greatest common divisor of two numbers.

Dynamic Array Example C++

A realistic C++ line counter

This program asks the user for a c++ source file. It displays the file’s linecount to the screen. Program exits on invalid input. This sourcefile is 90 lines of code(according to itself).
Each of the following counts as one line of code:

  1. Preprocessor directives
  2. if()
  3. while()
  4. do..while()
  5. switch()
  6. non-repeating semicolons

16 bit ALU Verilog design

[code title=”sep_alu.v Main module” collapse=”true”]
//B Turley
//16 bit ALU

timescale 1ns/100ps

module sep_alu(Y, cout16, cout15, rightout, leftout, A, B, s, cin, rightin, leftin);
output [15:0] Y;
output cout16, cout15;
output rightout, leftout;
input [15:0] A; //first input
input [15:0] B; //second input
input [3:0] s; //operation input
input cin; // carry in
input rightin, leftin; // shift inputs

wire [15:0] cvect;
wire [15:0] rvect;
wire [15:0] lvect;

alu_slice u0(Y[0], cvect[0], rvect[0], lvect[0], A[0], B[0], s, cin, rvect[1], leftin);
alu_slice u1(Y[1], cvect[1], rvect[1], lvect[1], A[1], B[1], s, cvect[0], rvect[2], lvect[0]);
alu_slice u2(Y[2], cvect[2], rvect[2], lvect[2], A[2], B[2], s, cvect[1], rvect[3], lvect[1]);
alu_slice u3(Y[3], cvect[3], rvect[3], lvect[3], A[3], B[3], s, cvect[2], rvect[4], lvect[2]);
alu_slice u4(Y[4], cvect[4], rvect[4], lvect[4], A[4], B[4], s, cvect[3], rvect[5], lvect[3]);
alu_slice u5(Y[5], cvect[5], rvect[5], lvect[5], A[5], B[5], s, cvect[4], rvect[6], lvect[4]);
alu_slice u6(Y[6], cvect[6], rvect[6], lvect[6], A[6], B[6], s, cvect[5], rvect[7], lvect[5]);
alu_slice u7(Y[7], cvect[7], rvect[7], lvect[7], A[7], B[7], s, cvect[6], rvect[8], lvect[6]);
alu_slice u8(Y[8], cvect[8], rvect[8], lvect[8], A[8], B[8], s, cvect[7], rvect[9], lvect[7]);
alu_slice u9(Y[9], cvect[9], rvect[9], lvect[9], A[9], B[9], s, cvect[8], rvect[10], lvect[8]);
alu_slice u10(Y[10], cvect[10], rvect[10], lvect[10], A[10], B[10], s, cvect[9], rvect[11], lvect[9]);
alu_slice u11(Y[11], cvect[11], rvect[11], lvect[11], A[11], B[11], s, cvect[10], rvect[12], lvect[10]);
alu_slice u12(Y[12], cvect[12], rvect[12], lvect[12], A[12], B[12], s, cvect[11], rvect[13], lvect[11]);
alu_slice u13(Y[13], cvect[13], rvect[13], lvect[13], A[13], B[13], s, cvect[12], rvect[14], lvect[12]);
alu_slice u14(Y[14], cvect[14], rvect[14], lvect[14], A[14], B[14], s, cvect[13], rvect[15], lvect[13]);
alu_slice u15(Y[15], cvect[15], rvect[15], lvect[15], A[15], B[15], s, cvect[14], rightin, lvect[14]);

assign cout16 = cvect[15];
assign cout15 = cvect[14];
assign rightout = rvect[0];
assign leftout = lvect[15];


[code title="sep_alu_tb.v Testbench" collapse="true"]

File: sep_alu_tb.v
Author: Jeremy Wood
Date: 6-8-04

Desc: This is the test bench for the ALU

modified 9-18-04 Added driveable left and right
shift inputs
modified 2-17-11 By B K Turley,
Corrected error with cin timing

timescale 1ns/100ps

module sep_alu_tb;

reg [15:0] A; // A Input
reg [15:0] B; // B Input
reg [3:0] s; // Operation select input
reg cin; // Carry input
reg rightIn; // Right Input from the shift operations
reg leftIn; // Left Input from the shift operations

wire [15:0] Y; // Y Ouput
wire cout16, cout15; // Carry Outputs
wire rightout, leftout; // Shift Outputs

// Invoke an instance of the test bench
sep_alu alu(Y, cout16, cout15, rightout, leftout, A, B, s, cin, rightIn, leftIn);

initial begin

$dumpvars(6, sep_alu_tb);

A <= 16’habcd;
B <= 16’h1234;
rightIn <= 1’b0;
leftIn <= 1’b0;

// Addition
#20 s <= 4’b0000;
cin <= 1’b0;

// Addition with Carry
#20 cin <= 1’b1;

// Subtract with Borrow
#20 s <= 4’b0001;
cin <= 1’b0;

// Subtraction
#20 cin <= 1’b1;

// Transfer A
#20 s <= 4’b0010;
cin <= 1’b0;

// Increment
#20 cin <=1’b1;

// Decrement A
#20 s <= 4’b0011;
cin <= 1’b0;

// Transfer A
#20 s <= 4’b0010;

// AND
#20 s <= 4’b0100;

// OR
#20 s <= 4’b0101;

// XOR
#20 s <= 4’b0110;

// Complement A
#20 s <= 4’b0111;

// Shift right A into F
#20 s <= 4’b1000;

// Shift left A into F
#20 s <= 4’b1100;

// 42 + -13
#20 A <= 16’d42;
B <= 16’b1111111111110011;
s <= 4’d0;

// -42 – -13
#20 A <= 16’b1111111111010110;
B <= 16’b1111111111110011;
s <= 4’d1;

// 70 + 80
#20 A <= 16’d70;
B <= 16’d80;
s <= 4’d0;

// -70 + -80
#20 A <= 16’b1111111110111010;
B <= 16’b1111111110110000;

// Clear signals for Simvision
#20 A <= 16’h0000;
B <= 16’h0000;

#20 $finish;

[code title=”alu_slice.v module” collapse=”true”]
//B Turley
//ALU one bit slice

timescale 1ns/100ps

module alu_slice(Y, cout, rightout, leftout, A, B, s, cin, rightin, leftin);
output Y;
output cout;
output rightout, leftout;
input A;
input B;
input [3:0] s;
input cin;
input rightin, leftin;

wire sum;
wire Bin, Lout;

mux_4to1 arithmatic(Bin, s[1:0], B, ~B, 1'b0, 1'b1);
mux_4to1 logicpart(Lout, s[1:0], A&B, A|B, A^B, ~A);
adder_1bit adder(sum, cout, A, Bin, cin);
mux_4to1 slicemux(Y, s[3:2], sum, Lout, rightin, leftin);

assign rightout = A;
assign leftout = A;


[code title="adder_1bit.v module" collapse="true"]
// 1 bit adder
// BK Turley

timescale 1ns/100ps

module adder_1bit(sum, cout, in1, in2, cin);

input in1;
input in2;
input cin;

output sum;
output cout;

assign cout = (in1 & in2) | (in1 & cin) | (in2 & cin);
assign sum = in1 ^ in2 ^ cin;


[code title=”mux_4to1.v module” collapse=”true”][/code]
// 4 channel, 1 bit mux
// BK Turley

`timescale 1ns/100ps

module mux_4to1(out, sel, in0, in1, in2, in3);

output out;
input [1:0] sel;
input in0;
input in1;
input in2;
input in3;

reg out;

always @( sel or in0 or in1 or in2 or in3)

case (sel)
2’b00 : out <= in0;
2’b01 : out <= in1;
2’b10 : out <= in2;
2’b11 : out <= in3;
default : out <= in0;


8 channel, 16 bit Verilog Multiplexer

[code title=”mux_8to1_16bit.v” collapse=”true”]
// 8 channel mux
// BK Turley

timescale 1ns/100ps

module mux_8to1_16bit(out, sel, in0, in1, in2, in3, in4, in5, in6, in7);

input [2:0] sel;
input [15:0] in0;
input [15:0] in1;
input [15:0] in3;
input [15:0] in4;
input [15:0] in5;
input [15:0] in6;
input [15:0] in7;
output [15:0] out;

reg [15:0] out;

always @( sel or in0 or in1 or in2 or in3
or in4 or in5 or in6 or in7)

case (sel)
3'b000 : out <= in0;
3'b001 : out <= in1;
3'b010 : out <= in2;
3'b011 : out <= in3;
3'b100 : out <= in4;
3'b101 : out <= in5;
3'b110 : out <= in6;
3'b111 : out <= in7;
default : out <= in0; // channel 0 is selected on high impedence input


[code title="mux_8to1_16bit_tb.v" collapse="true"]

// B. Turley

timescale 1ns/100ps

module mux_8to1_16bit_tb;

reg [2:0] mux_sel;
reg [15:0] mux_in0;
reg [15:0] mux_in1;
reg [15:0] mux_in2;
reg [15:0] mux_in3;
reg [15:0] mux_in4;
reg [15:0] mux_in5;
reg [15:0] mux_in6;
reg [15:0] mux_in7;
wire [15:0] mux_out;

mux_8to1_16bit mux(mux_out, mux_sel, mux_in0, mux_in1, mux_in2,
mux_in3, mux_in4, mux_in5, mux_in6, mux_in7);

initial begin

$dumpvars(2, mux_8to1_16bit_tb);

mux_in0 <= 16’h0000;
mux_in1 <= 16’h0001;
mux_in2 <= 16’h0002;
mux_in3 <= 16’h0003;
mux_in4 <= 16’h0004;
mux_in5 <= 16’h0005;
mux_in6 <= 16’h0006;
mux_in7 <= 16’h0007;
mux_sel <= 3’b000;

#20 mux_sel <= 3’b001;
#20 mux_sel <= 3’b010;
#20 mux_sel <= 3’b011;
#20 mux_sel <= 3’b100;
#20 mux_sel <= 3’b101;
#20 mux_sel <= 3’b110;
#20 mux_sel <= 3’b111;
#20 mux_sel <= 3’b000;

#20 $finish;


Verilog 16 bit register with testbench.

[code title=”reg_16bit.v code” collapse=”true”]//16 bit Register by B Kyle Turley

timescale 1ns/100ps

module reg_16bit (out, in, load, clear, clk);
input   [15:0]   in;
input           load;
input           clear;
input           clk;
output  [15:0]   out;

reg     [15:0]   Q;

always @(posedge clk)
if(clear == 1'b1) // If clear is high, it has priority
Q <= 16'b000000000000000;
else if(load == 1'b1) // load has the next highest
Q <= in;
Q <= Q;

/* Set output equal to the internal state */
assign out = Q;



[code title="reg_16bit_tb.v code" collapse="true"]timescale 1ns/100ps

module reg_16bit_tb;

reg [15:0] reg_input;
reg reg_load;
reg reg_clear;
reg clk;

wire [15:0] reg_out;
integer fid;

reg_16bit register(reg_out, reg_input, reg_load, reg_clear, clk);

initial begin
clk = 1’b0;
forever #10 clk <= ~clk;

initial begin

fid = $fopen("./reg_16bit.out");
$fmonitor(fid, $time, " out = %h, in = %h, load = %b, clear = %b",
reg_out, reg_input, reg_load, reg_clear ) ;

$dumpvars(2, reg_16bit_tb);

reg_clear <= 1’b1;
reg_load <= 1’b0;
reg_input <= 16’hABCD;
#20 reg_clear <= 1’b0;
#20 reg_load <= 1’b1;
#20 reg_load <= 1’b0;
#20 reg_input <= 16’h1234;
#20 reg_load <= 1’b1;
#20 reg_load <= 1’b0;
reg_input <= 16’h0000;
reg_clear <= 1’b1;
#20 reg_clear <= 1’b0;
#20 $finish;


Can’t use a string in a C++ switch statement? Here is a simple alternative.

Many programmers are surprised to find that switch statements aren’t compatible with strings in C/C++.

When attempting to compile, you will see an error:

Visual Studio 2010 —–  error C2450: switch expression of type ‘std::string’ is illegal

Netbeans 6.9.1 —– error: switch quantity not an integer

Here is an example of invalid code

The problem is that strings are not a basic type in the C++ language. Whenever a C++ programmer uses basic variables types like int, bool, and char, nothing extra needed. But when a C++ programmer wishes to use strings in a program, they must add #include <string> to the top of the code to enable that functionality. Basic switch statements don’t have the capability to understand “add on” features such as strings and other filestreams.

There is still hope. The people who created the string library were kind enough to include a function to compare strings – strcmp(). The string compare function can be used along with if..else statements to achieve the same logic as a switch statement.

This is the same logic as before without using a switch statement: