Reverse engineering a 16 character display using an Atmel 328p.

Switches and interrupts on a PSoC 1 Microcontroller

I. Introduction / Summary

The most practical way for a microcontroller to retrieve input is via interrupt.  The vast majority of modern processors have interrupt functionality.  This functionality allows a processor to work on background tasks while no input has happened. Once input is detected, the processor diverts its attention to react, then returns to where it left off after the interrupt has been serviced.

II. Description and Circuit Diagrams

An optical encoder is connected to VCC and ground to provide power to its internal emitters, detectors, and squaring circuitry.  The encoders outputs are connected to P1[4] and P1[5] on the PSoc board. P2[0-6] are connected to a LCD on the evaluation board.

Using this setup, we will display to the LCD a number between 0 and 100 that reflects the direction of the encoder rotation.

Capture1

III. Description of Software

The software routine enables interrupts, starts the LCD, and takes a measurement of the B output of the rotary encoder upon startup.  It then simply executes an infinite loop with no consequences.  The only way to leave this loop is via an interrupt triggered by a change in either the A or B inputs from the rotary encoder.  Once a change in input is detected, the execution jumps to the interrupt service routine named PSoC_GPIO_ISR_C(void). This ISR takes a measurement of the A input, clears the LCD, then performs an XOR operation on the current A and the previously stored B to determine whether the rotary encoder was turned clockwise or counter clockwise.  A count variable (initially = 50) is incremented or decremented accordingly within the explicitly defined limits of 0~100. The LCD is updated to display the count variable. Finally the current value of B is stored to be used during the next execution of the ISR.

IV. Validation and Testing

The setup was tested by turning the rotary encoder clockwise and counter-clockwise while observing the LCD to see the count being updated.  The encoder was moved to both the upper and lower limits to ensure that the LCD display correctly prevented any value < 0 or > 100 from being displayed.

V. Program listing

Verilog model of a control unit for the SEP (Simple Educational Processor)

[code title=”View Code: sep_cu.v” collapse=”true”]
module cu(clk, reset, IRin, C, SC_Val);

input clk, reset;
input [15:0] IRin;

output [14:0] C;
output [3:0] SC_Val;

wire [7:0] D;
wire [7:0] T;

wire w1;

decoder_df IR_decoder(IRin[14],IRin[13],IRin[12], 0, D);
decoder_df Cnt_decoder(SC_Val[2],SC_Val[1],SC_Val[0], 0, T);
SecCounter SC(SC_Val, clk, w1, 0);

or (w1,C[8],reset);

assign
C[0] = T[0] | T[2] | (~D[7] & IRin[15] & T[3]),
C[1] = D[4] & T[4],
C[2] = T[1],
C[3] = D[2] & T[4],
C[4] = D[2] & T[5],
C[5] = T[1],
C[6] = T[1] | (~D[7] & IRin[15] & T[3]) | (D[2] & T[4]),
C[7] = D[3] & T[4],
C[8] = (D[2] & T[5]) | (D[3] & T[4]) | (D[4] & T[4]),
C[9] = T[1] | T[2] | T[3] | (T[4] & D[2]) | (T[4] & D[3]),
C[10] = T[0] | T[1] | T[3] | (T[4] & D[2]),
C[11] = T[1] | T[2] | T[3] | (T[4] & D[2]) | (T[4] & D[4]),
C[12] = 0,
C[13] = 0,
C[14] = 0;

endmodule

module decoder_df (A,B,C,E,D);
input A,B,C,E;
output [7:0] D;
assign D[0] = (~A & ~B & ~C & ~E),
D[1] = (~A & ~B & C & ~E),
D[2] = (~A & B & ~C & ~E),
D[3] = (~A & B & C & ~E),
D[4] = (A & ~B & ~C & ~E),
D[5] = (A & ~B & C & ~E),
D[6] = (A & B & ~C & ~E),
D[7] = (A & B & C & ~E);
endmodule

module SecCounter(count, CLK, RST, INC);
parameter n = 4;

output [n-1:0] count;
reg [n-1:0] count;
input CLK;
input RST;
input INC;

// Increment count on clock
always @(negedge CLK)
if (RST)
count = 0;
else if (~INC)
count = count + 1;

endmodule
[/code]

Verilog Clock and Oscillator

The clock signal is essential when designing sequential circuits, the following two code examples demonstrate how to produce a clock signal for your FPGA projects. These modules could also be used to produce square wave oscillations for other purposes such as audio tones.

[sourcecode]

module Clk_Signal (clock); // Verilog 1995
parameter delay = 5;
output clock;
reg clock;</code>

initial begin
clock = 0;
forever #delay clock = ~clock;
end
endmodule

module Clk_Signal #(parameter delay = 5) (output reg clock); // V2001

initial forever #delay clock = ~clock;
endmodule

[/sourcecode]

How to do structs in MIPS assembly

[code title=”View Source Code:” collapse=”true”]
# Learning Objectives:
# Functions, arrays, structures.

############################################
#### C++ Code
############################################

#void DisplayTemps(Temp temps[], int len);
#
#struct Temp {
# int lo;
# int hi;
#};
#
#int main() {
# Temp temps[] = { {40, 74}, {45, 80}, {60, 91} };
#
# DisplayTemps(temps, 3);
#
# return (0);
#}
#
#void DisplayTemp(Temp temps[], int len) {
# cout < < "Listing of (lo, hi) temps:"
# << endl;
# for (int i = 0; i < len; i++) {
# cout << temps[i].lo
# << " "
# << temps[i].hi
# << endl;
# }
#}
###

###########################################
#### MIPS code
###########################################

.data

words: .asciiz "Listing of (lo, hi) temps:n"
somespace: .asciiz " "
newline: .asciiz "n"

temps:
# declare an array of structs that is preloaded with values
.word 40,74 #( Just like a 2d array )
.word 45,80
.word 60,91

.text

main:

#######
addiu $sp, $sp, -4
sw $ra, 0($sp)
S
la $a0, temps # DisplayTemps(temps, 3);
addi $a1, $zero, 3 #
jal DisplayTemps ####

lw $ra, 0($sp)
addiu $sp, $sp, 4
jr $ra

DisplayTemps:

###############

li $v0, 4 # print_string
la $a0, words # " Listing of (lo, hi) temps:"
syscall

# FOR LOOP

la $t0, temps #$t0 holds the address of the 1st element
li $t1, 1 # iterator = 1
#a0 holds the current elements value

for:

bgt $t1, $a1, exitfor # exit if iterator > a1 (len)

li $v0, 1 # print_int
lw $a0, ($t0)
syscall

li $v0, 4 # print_string
la $a0, somespace # " "
syscall

li $v0, 1 # print_int
add $t0, 4 # increment the index
lw $a0, ($t0)
syscall

add $t0, 4 #increment index again
lw $a0, ($t0)

li $v0, 4 # print_string
la $a0, newline # "n"
syscall
#Increment iterator
add $t1, 1

j for

exitfor:

jr $ra

[/code]